Offset cancellation cell

 

1000BaseT DSP Model

We provide a complete DSP Front End model solution for Gigabit copper physical layer which includes:

  • Choice of MatlabTM/Simulink or C++ DSP system behavioral model.
  • HDL at block structural level.
  • 7 Bit ADC compatible.
  • Both bit level and floating point models.
  • Efficient Tapered LMS resolution.
  • Exploration of resolution / filter length tradeoffs. 
  • Matlab cable and plant models developed from over 1800 individual plant measurements.
  • Supports simple resistive hybrid.
  • Option for baud rate or 2x oversampled system.
  • Detailed documentation.
  • Support services for design integration.
  • IEEE compliance in function and interface signaling.

Design Functions:

  • Digital Timing Recovery.
  • Automatic Gain Control System.
  • Decision Feedback Equalizer.
  • Echo Cancellation
  • NEXT Cancellation.
  • Offset Cancellation.
  • DC Wonder Correction.
  • Transmit filtering.
  • State Controller.
  • Models of Analog Front End Functions.
  • Extensive cable and plant models.

 Call today for a demonstration!

 

Basic Transceiver System (One Channel)

 

System Simulator Screen Shot

System Simulation Results

 

 

Master Convergence with 100 meter Cable, Echo, and NEXT

(CHDL Simulation Output)
The simulator output (left) shows typical output from the "CHDL" C++ behaviour system model. 
The traces are color coded as follows:
  •       RED :  Channel input after echo and NEXT cancel.
  •     BLUE :  Echo/NEXT canceller output.
  • GREEN :   Input to slicer.

This is a worst case simulation with a 100 meter cable model, echo, NEXT, and timing recovery. 

The master mode startup phases can clearly be seen. Namely: 

  1. Echo cancellation with no received signal.
  2. Timing recovery and DFE convergence.
  3. Switch to five level received signal.

The following is the detail of timing convergence with a frequency offset between transmitter and receiver:

gbTimingFoil.png (65308 bytes)


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