Foundry Specification
PACKAGE('package_name');
Object type Pascal procedure.
Status Base code.
User level 4
Description
Used to define the package the design is going to be mounted in. The
purpose of this procedure is to inform the foundry on device packaging as
well as checking that the device is valid for the number and position of
IO's, power and ground pins extra. These checks are only active however in
release mode. The following packages are valid in v0r1:
PDIP24 Dual in line plastic
PDIP28
PDIP40
PLCC68 Plastic leaded chip carrier
PLCC84
Constraints
Package name must be valid. Must appear before DEFPIN.
Examples
1) PACKAGE('PDIL24'); {specify a 24 pin dual in line packager}
2) package('CLCC84'); {specify an 84 pin chip carrier}
See also
PIN, RELEASE
L2I v0r1 Draft copy Page 3.1
Foundry Specification
PHONE_NUMBER('designers_phone_number');
Object type Pascal procedure.
Status base code
User level 4
Description
This statement is used to specify the designers phone number so that he
or she can be contacted if a problem if found with the design. Having this
information to hand saves time at the foundry and helps keep all of the
design information in one place. When release checks are done this
statement is required. It may appear anywhere in the source file.
Constraints
The input string to this procedure must be at least 5 characters long.
Examples
1) PHONE_NUMBER('0344 525252');
2) PHONE_NUMBER('01 1234556');
Typical errors
1) phone_number(Ol 1234567); {quotes are needed}
2) phone_number('5252'); {number is too short}
See also
DESIGNER, RELEASE
Draft copy Page 3.2
Foundry Specification
ADDRESS(' designers_address ');
Object type : Pascal procedure.
Status : base code
User level : 4
Description
This statement is used to specify the designers address so that he or she
can be contacted if a problem if found with the design.
Constraints
The input string to this procedure must be at least 15 characters long
and contain at least 2 commas.
Examples
1) ADDRESS('Mount Lane, Bracknell, BERKS');
Typical errors
1) ADDRESS( 67 Church Rd, Reading, BERKS ); {no quotes}
2) ADDRESS('ES2'); {not long enough and no commas}
See also
DESIGNER, RELEASE
L2I v0r1 Draft copy Page 3.3
Foundry Specification
DESIGNER(' designers_name ');
Object type : Pascal procedure.
Status : Available
User level : 4
Description
This statement is used to specify the designers name so that he or she
can be contacted if a problem if found with the design, Having this
information to hand saves time at the foundry and helps keep all of the
design information in one place. When release checks are done this
statement is required. It may appear anywhere in the source file.
Constraints
The input string to this procedure must be at least 10 characters long.
Examples
1) DESIGNER('Robert Heaton');
2) DESIGNER('Valerie Daykin');
Typical errors
1) designer(Steven Lewis); {quotas are neaded}
2) designer('Steve'); {name is too short}
See also
RELEASE, PHONE-NUMBER
L2I v0r1 Draft copy Page 3.4
Foundry Specification
DEFPIN('sig_name',pin_number);
Object type : Pascal procedure.
Status : bass code
User level : 4
Description
This statement is used to specify the mapping between signal names and
package pin numbers in machine readable form. In release mode checks are
done to ensure that pinning is valid for the specified package, VSS and
VDD pins must also be specified using the PIN statement and these are also
checked for valid position and number. Normally power and ground pins will
be called "$VDD" and "$VSS" since the $ sign makes these into global
signals. Power and ground are required in release mode.
Constraints
Only one signal is specified per PIN statement. The sig_name must exist.
Examples
1) DEFFIN('reset',12); {reset is pin 12}
2) DEFPIN('VSS', 28 ); {VSS is pin 28}
Typical errors
1) DEFPIN(reset,4); {reset not in quotes}
2) DEFPIN('VDD',356); {pin not on package!}
See also
RELEASE, PACKAGE
L2I v0r1 Draft copy Page 3.5
Foundry Specification
RELEASE;
Object type : Pascal procedure.
Status : limited checks till v1r1
User level : 4
Description
This statement is used to turn on the L2I release mode in which a range
of checks of design quality and integrity are enabled. These checks
include network IO type checks, list of unconnected inputs, minimum
toggled nodes, maximum test patterns, static simulation, and non
appearance of a range of development only features.
Constraints
Must appear before the NETSTART statement.
Examples
1) RELEASE;
Typical errors
1) RELEASE { no ; }
See also
PACKAGE, DEFPIN
L2I v0r1 Draft copy Page 3.6
Library Elements
BASE LIBRARY ELEMENT LIST
The following library elements are included in the basic L2I code. All of
the bass elements correspond with base library elements from the Lattice
Logic system. Gross timing only is included in v0rl and the timings are
based broadly on the timings within the 2u System cell library. All
library elements are functionally translatable to System Call and Lattice
libraries. The setup, hold and minimum Pulse widths on all L2I flip flop
calls are guard banded to improve design quality checking.
Name Draft name Syntax
iono iono I('gx, iono, externalin, out');
oono ocno I('gx, ocno,in, externalout');
invl not I('gx, invl, in, out');
inv4 I('gx, inv4, in, out');
nand2 nand I('gx,nand2, inl, in2, out');
nand3 nand I('gx,nand3, inl,in2,in3,out');
nand4 nand I('gx,nand4,inl,in2,in3,in4,out');
nand5 nand I('gx,nand5,inl,in2,in3,in4,in5,out');
nor2 nor I('gx,nor2,inl,in2,out');
nor3 nor I('gx,nor3,inl,in2,in3,out');
nor4 nor I('gx,nor4,inl,in2,in3,in4,out');
and2 and I('gx,and2,inl,in2,out');
and3 and I('gx,and3,inl,in2,in3,out');
and4 and I('gx,and4,inl,in2,in3,in4,out');
and5 and I('gx,and5,inl,in2,in3,in4,in5,out');
or2 or I('gx,or2,inl,in2,out');
or3 or I('gx,or3,inl,in2,in3,out');
or4 or I('gx,or4,inl,in2,in3,in4,out');
xor xor I('gx, xor, a, b, out');
aoi I('gx, aoi, a, b, c, d, out');
dffn dffn I('gx,dffn,clk,data,nset,nclear,q,nq');
L2I v0r1 Draft copy Page 4.1
Plans
FUTURE PLANS
* Full documentation including library writers guide.
* Netlist conversion programs and library for a PC schematic capture
system such as SCHEMA which costs less than $500.
* CRITICAL and GROUP statements for control of layout.
* An EDIF library and EDIF/L2I conversions to allow L2I to be used with
any EDIF comparable schematic capture package.
* WRITE-WAVE statement for writing a waveform file which can be plotted
on a matrix printer or on screen.
* RAM, ROM and PLA primitives in library.
* Fault modeling for versions on large machines with > 1MB of address
space.
* Support a range of machines: PC,SUN,VAX,APPOLO as needed,
* Lattice tlf and drv outputs.
L2I v0r1 Draft copy Page 5.1
Page created by: heaton@home.com
Changes last made on: Wed Jun 12 11:32:04 1996
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